PIC16C63A-04I/SO【PDF 81/184 页】IC MCU OTP 4KX14 PWM 28SOIC

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171

SAM7S Series [DATASHEET]

6175M–ATARM–26-Oct-12

ters, R0 to R7, must be saved before being used, and restored at the end (before the next step). Note that

if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during

this phase in order to de-assert the interrupt source 0.

Finally, the Link Register R14_fiq is restored into the PC after decrementing it by four (with instruction

SUB PC, LR, #4

for example). This has the effect of returning from the interrupt to whatever was being

executed before, loading the CPSR with the SPSR and masking or unmasking the fast interrupt depend-

ing on the state saved in the SPSR.

Note:

The “F” bit in SPSR is significant. If it is set, it indicates that the ARM core was just about to mask FIQ interrupts when

the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ

is masked).

Another way to handle the fast interrupt is to map the interrupt service routine at the address of the ARM vector

0x1C. This method does not use the vectoring, so that reading AIC_FVR must be performed at the very beginning

of the handler operation. However, this method saves the execution of a branch instruction.

23.7.4.5

Fast Forcing

The Fast Forcing feature of the advanced interrupt controller provides redirection of any normal Interrupt source on

the fast interrupt controller.

Fast Forcing is enabled or disabled by writing to the Fast Forcing Enable Register (AIC_FFER) and the Fast Forc-

ing Disable Register (AIC_FFDR). Writing to these registers results in an update of the Fast Forcing Status

When Fast Forcing is disabled, the interrupt sources are handled as described in the previous pages.

When Fast Forcing is enabled, the edge/level programming and, in certain cases, edge detection of the interrupt

source is still active but the source cannot trigger a normal interrupt to the processor and is not seen by the priority

handler.

If the interrupt source is programmed in level-sensitive mode and an active level is sampled, Fast Forcing results in

the assertion of the nFIQ line to the core.

If the interrupt source is programmed in edge-triggered mode and an active edge is detected, Fast Forcing results

in the assertion of the nFIQ line to the core.

The Fast Forcing feature does not affect the Source 0 pending bit in the Interrupt Pending Register (AIC_IPR).

The FIQ Vector Register (AIC_FVR) reads the contents of the Source Vector Register 0 (AIC_SVR0), whatever the

source of the fast interrupt may be. The read of the FVR does not clear the Source 0 when the fast forcing feature

is used and the interrupt source should be cleared by writing to the Interrupt Clear Command Register

(AIC_ICCR).

All enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in

edge-triggered mode must be cleared by writing to the Interrupt Clear Command Register. In doing so, they are

cleared independently and thus lost interrupts are prevented.

The read of AIC_IVR does not clear the source that has the fast forcing feature enabled.

The source 0, reserved to the fast interrupt, continues operating normally and becomes one of the Fast Interrupt

sources.

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